1. Field of the Invention
The present invention relates to semiconductor devices and method for manufacturing semiconductor devices, and more particularly, to a capacitor of a semiconductor device and a manufacturing method thereof.
2. Description of the Related Art
Capacitors of highly integrated memory semiconductor devices, such as a large capacity dynamic random access memory (DRAM) and a ferroelectric random access memory (FRAM), include dielectric layers made of materials such as PZT (PbZrTiO3) and BST (BaSrTiO3), which have a high dielectric constant. Electrodes in these capacitors are often made of a metal from the platinum group or an oxide of a platinum group metal. However, forming and dry etching of platinum group metals and the their oxides often present difficulties. Further, the metals and oxides are prone to react with semiconductor substrates or polysilicon plugs. Accordingly, a diffusion barrier layer is required between the conductive layer and semiconductor materials such as polysilicon.
FIG. 1 illustrates a semiconductor device including a conventional capacitor having a dielectric layer with high dielectric constant. Referring to FIG. 1, a first insulating layer 3 having a contact hole 2 is on a semiconductor substrate 1, and a polysilicon contact plug 5 and a tantalum (Ta) diffusion barrier layer 7 are in contact hole 2. An etch stop layer 9 and a third insulating layer 11 are sequentially formed on first dielectric layer 3 overlying semiconductor substrate 1 and patterned to expose diffusion barrier layer 7 and adjacent portions of first insulating layer 3.
A storage node 13 is on the inner wall of the opening in third insulating layer 11 and on the exposed portions of diffusion barrier layer 7 and first insulating layer 3. A BST dielectric layer 15 is on storage node 13, and a ruthenium (Ru) plate node 17 is on dielectric layer 15.
Diffusion barrier layer 7 suppresses reactions between storage node 13 and contact plug 5. However, in the conventional capacitor of FIG. 1, the storage node 13 is thin, and deposition of dielectric layer 11 or subsequent annealing can oxidize diffusion barrier layer 7 into a Ta2O5 insulating layer. Thus, the contact resistance between storage node 13 and substrate 1 increases. Further, the chemical mechanical deposition that forms ruthenium storage node 13 leaves an irregular surface morphology, resulting in regions of storage node 13 with concentrated electric fields when the capacitor is in use. These high electric field regions can increase leakage current of the capacitor.
In accordance with the present invention, a method is provided for manufacturing a capacitor of a semiconductor device. The method includes: forming a first insulating layer having a contact hole on a semiconductor substrate; forming a diffusion barrier layer in the contact hole, wherein the diffusion barrier layer electrically connects to the semiconductor substrate; forming a second insulating layer and a third insulating layer sequentially on the first insulating layer, wherein a hole is formed in the second insulating layer and third insulating layer to expose the diffusion barrier layer; forming a conductive layer on the semiconductor substrate such that the conductive layer covers the inner wall of the hole in the second insulating layer and third insulating layer; forming an insulating fill layer that fills the remainder of the hole containing the conductive layer; removing upper portions of the fill layer until the third insulating layer is exposed but a portion of the fill layer remains in the hole; removing the third insulating layer to expose the second insulating layer; forming a dielectric layer on the semiconductor substrate, wherein the dielectric layer covers remaining portions of the fill insulating layer, the second insulating layer, and the conductive layer; and forming a plate node on the dielectric layer.
Forming the conductive layer on the inner surface of a hole in the insulating layers provides the conductive layer with a smooth surface that is later covered by the dielectric layer. Additionally, the presence""s of the second insulating layer between storage electrodes and filling the cavity in the conductive layer prevents diffusion of oxygen and oxidation of the diffusion barrier layer.